1. Field of the Invention
The present invention is related to a power factor correction device, and more particularly, to a power factor correction device enhancing a power factor and reducing a conduction loss by simultaneously applying two “set” trigger schemes of an SR flip-flop.
2. Description of the Prior Art
A power factor is a ratio of an effective power to a total dissipated power, and is utilized for estimating electrical power efficiency. In general, the greater the power factor, the better the electrical power efficiency. Therefore, a power supply usually includes a power factor correction device to ensure that waveforms of an alternating current (AC) and an AC voltage are consistent and suppress undesired harmonics, so as to enhance power efficiency. Most power factor correction devices can be divided into two categories: passive type and active type. A passive power factor correction device is composed of passive components, such as inductors, capacitors, etc., and is designed for processing a low frequency (50-60 Hz) AC input with at most a 75-80% power factor. On the contrary, an active power factor correction device is composed of active components, such as power transistors, and is utilized for regulating a waveform of an input current to be consistent with a waveform of an input voltage. In theory, the active power factor correction device can achieve almost a 100% power factor. For that reason, most power supplies employ the active power correction device, especially in high-power applications.
Please refer to FIG. 1A, which is a schematic diagram of an active power factor correction device 10 of the prior art. The power factor correction device 10 mainly includes a diode bridge rectifier 100, an intermediate inductor 110, a power transistor 112, a set/reset (SR) flip-flop 114, a sensing inductor 116, a multiplier 118, an error amplifier 120, a comparator 122 and dividing circuits 130, 140. The diode bridge rectifier 100 is utilized for converting an AC input voltage VINAC into a direct current (DC) input voltage VINDC. Combination of the intermediate inductor 110 and the sensing inductor 116 functions as a voltage transformer for setting a latch result LAT of the SR flip-flop 114 to “1” when an inductor current IL of the intermediate inductor 110 decays to zero to enable the power transistor 112. Once the power transistor 112 is enabled, the inductor current IL increases, causing a source voltage VS of the power transistor 112 to rise. In addition, the dividing circuits 130, 140 are respectively utilized for generating a divided voltage Vdiv1 of the DC input voltage VINDC and a divided voltage Vdiv2 of a DC output voltage VOUTDC. The error amplifier 120 compares the divided voltage Vdiv2 with a reference voltage VREF to generate a comparison result COMP. Next, the multiplier 118 multiplies the divided voltage Vdiv1 by the comparison result COMP to generate a voltage product MUL. Finally, the comparator 122 compares the voltage product MUL with the source voltage VS to determine whether to reset the latch result LAT of the SR flip-flop 114 to “0” accordingly. When the source voltage VS is greater than the voltage product MUL, the latch result LAT is “0”, and the power transistor 112 is disabled to reduce the inductor current IL. Such a control mode is called a “Boundary Mode (BM)”.
In short, by periodically setting and resetting the latch result LAT, the waveform of the average current IL—avg of the inductor current IL can follow the waveform of the DC input voltage VINDC, as illustrated in FIG. 1B. Despite the excellent power factor shown in FIG. 1B, a root mean square (RMS) value of the inductor current IL is extraordinarily high, and therefore it is disadvantageous to employ the power factor correction device 10 in applications with serious conduction loss.
Please continue to refer to FIG. 2A, which is a schematic diagram of another active power factor correction device 20 of the prior art. The power factor correction device 20 is an enhanced version of the power factor correction device 10, and differs only in a timer 200 replacing the sensing inductor 116 shown in FIG. 1A. The timer 200 is utilized for clocking, since the latch result LAT is reset (LAT:1→0), and triggering the SR flip-flop 114 to set the latch result LAT to “1” after a default period. As a result, a waveform of the average current IL—avg of the inductor current IL can follow a waveform of the DC input voltage VINDC, as illustrated in FIG. 2B. Such a control mode is called “Fixed Off-Time (FOT) control”.
Compared to the power factor correction device 10, the power factor correction device 20 benefits from a lower RMS value of the inductor current IL, i.e. lower conduction loss. However, since the power transistor 112 is disabled during the default period, which is fixed, the power factor correction device 20 enters a discontinuous conduction mode (DCM) from a continuous conduction mode (CCM) when the average current IL—avg of the inductor current IL approaches zero, causing distortion in the average current IL—avg and decay in the power factor. That is, neither of the power factor correction devices 10, 20 can simultaneously benefit from “high power factor” and “low conduction loss”.
Therefore, enhancing the power factor correction device to achieve both “high power factor” and “low conduction loss” has been a major focus of the industry.